A frame synchronizer detects a periodic synchronization pattern present in a serial data stream so as to identify the beginning of a data frame. Within each data frame are a number of data words which each consist of a predetermined number of data bits. Typically, a data word contains eight bits. The synchronization pattern may be contained within a single data word or may consist of a number of sequential data words. Detection of the synchronization pattern involves matching the predetermined pattern to a substantially similar (so as to allow for errors) or identical group of bits in the incoming data stream.
The continuing evolution of integrated electronic components and advances in data communication technology have enabled faster and faster data communication rates. High speed data communication applications, including fiber optic communication systems and space data communication systems (such as satellite communications), may operate at rates exceeding 1 Gigabit/second (Gbps). Specialized electronics are often utilized to meet the demands of such high speed applications. Emitter coupled logic (ECL) components may be utilized although they are more expensive and have a higher power consumption than complimentary metal oxide silicon (CMOS) components. However, CMOS components are typically not fast enough to accommodate these high speed communication applications.
Another possible implementation of high speed data communication electronics utilizes application specific integrated circuits (ASIC's) which typically employ gallium arsenide (GaAs) technology. These specialized electronic circuits require significant design and development time and are very expensive to manufacture. Thus, it would be desirable to employ standard CMOS components to implement a high speed frame synchronizer due to their relatively low cost, common availability and low power consumption.
Space data communication systems have unique design considerations. Efforts are taken to minimize power consumption by transmitting equipment since space systems often utilize solar power. Often, data is captured and recorded by a satellite data recorder utilizing magnetic tape reels and is not transmitted until some later time to an Earth ground station. The data is then transmitted in reverse order so that the tape reel does not have to be rewound. Thus, a frame synchronizer located at the ground station must detect reverse data for proper synchronization.
A frame synchronizer used in space data communications must also detect forward data which is transmitted in real-time as it is captured. Furthermore, the system should be capable of detecting inverted or true data signals. Inverted data signals may result from a phase shift in the received data signal since the demodulator at the receiver may lock in a true or inverted state relative to the transmitter.
High speed data communication requires efficient and reliable fault detection and correction techniques, especially when data is transmitted in real time, since retransmission may be difficult or impossible. A number of factors may be responsible for various data errors which may occur. These errors include random errors as well as burst errors. One such factor in space data communications is the considerable distance which the data must travel through the atmosphere before arriving at the ground station receiver. Therefore, it is desirable for a frame synchronizer to tolerate a number of errors without losing synchronization, while also correcting any errors which may be present.
Typical frame synchronizers have a number of operating modes. These may include a "hunt" or "search" mode which attempts to identify the synchronization pattern in the incoming data stream as well as a "Lock" mode and a "Check" or "Verify" mode. Once the synchronization pattern has been identified (with some certainty) the synchronizer enters the Verify mode and looks to the next frame to see that the pattern has indeed been located. If the pattern does not occur where it is anticipated then the system returns to Search mode. Sometimes, the pattern may be shifted by a bit from its anticipated position at the beginning of the frame. This is known as a bit slip. It is desirable for a frame synchronizer to be able to tolerate some bit slips so that synchronization is not easily lost.